This invention relates to methods of manufacture of FET semiconductor device, and more particularly to methods of manufacture of SOI CMOS structures and devices manufactured thereby.
Scaling (reduction in dimensions) of Silicon-On-Insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) structures requires scaling of the silicon thickness to achieve device performance targets (short channel control, etc.).
FIG. 1A shows the typical structure of a prior art SOI device 10 prior to epitaxial growth of the epitaxial, raised source/drain regions 28S/28D of FIG. 1B on the surface of semiconductor substrate comprising the thin silicon layer 12 of the device 10. The substrate of the device 10 includes a thin silicon layer 12 formed on a Buried OXide (BOX) layer 11. A gate electrode stack is formed above the thin silicon layer 12. The gate electrode stack includes a gate dielectric (gate oxide) layer 14, a gate electrode 18 composed of polysilicon formed above the gate dielectric layer 14, and a hard mask 22 formed above the gate electrode 18. Sidewall spacers 16 composed of silicon oxide have been formed on the sidewalls of the gate electrode 18 and are intended to cover the sidewall surfaces of the gate electrode 18 entirely.
Note the pull-down of the spacers 16 below the hard mask 22 resulting in exposure of some of the sidewall surfaces of the polysilicon at the top corners of the gate electrode 18. This is typical of the problem of spacer pull-down due to normal processing (spacer overetch, etc.). Reduction of this pull-down by means known heretofore would tend to reduce the robustness of the overall process (residual nitride, etc).
FIG. 1B shows the device 10 of FIG. 1A after the epitaxial growth of the epitaxial raised source 28S and the epitaxial raised drain 28D on the surface of the thin silicon layer 12 of the substrate of the device 10.
The problem which is illustrated by FIG. 1B is that the exposure of the upper corners of the gate electrode 18 has led to spurious growth of epitaxial silicon nodules 28T which are seen in the regions exposed at the top corners of the gate electrode 18, as shown on either side thereof.
The processing requirement in the past has been to protect the polysilicon of the gate polysilicon 18 with spacers 16 for the purpose of avoiding the formation of spurious epitaxial growth of such epitaxial silicon nodules during the formation of epitaxial, raised source drain regions.
Silicidation is the process of converting a Silicon (Si) material to a silicide material. As a result of the silicidation process, the consumption of silicon thereby depends on the type of silicide being formed. For example, formation of cobalt silicide (CoSi) consumes more silicon than formation of nickel silicide (NiSi). Raised source and drain structures are required in SOI CMOS because the silicon layer in which the device is formed is reduced in thickness. This is the primary enabling element, i.e. strategy, for achieving continued reduction in silicon thickness.
The process of formation of raised source/drain regions suffers from a very limited process window. Any exposure of the gate polysilicon 18 through either the hard mask 22 and/or above the sidewall spacers 16 results in unwanted epitaxial growth of silicon nodules 28T on the upper surfaces of the gate electrode 18 where they are exposed.